One method of integrated circuit interconnection is called flip-chip bonding. Here bumps of solder or other conductive material are deposited onto conductive pads of a semiconductor wafer or chip. After separation of individual dies from the wafer the individual dies or chips are turned upside down and a bumps are properly align with a metallization pattern on another substrate. The aligned bumps are then join to appropriate points on the pattern.
Conventional interconnect methods employed lead base solders for connecting flip-chips to substrates. As the structural dimensions of electronic devices get smaller the use of sphere shaped solder bumps is disadvantageous because it may be difficult to achieve a fine pitch between adjacent interconnects without bridging which causes electrical shorting. Therefore it is desirable to provide an improved interconnect system to achieve finer pitch with minimum probability of bump bridging period.
The increasing demand for integration generally requires much more dense interconnects between chip to substrate as well as between chip to chip. The conventional solder bump plating technology is the technology of choice for pitches greater than 80 microns. For finer pitches and larger interconnect densities, pillar bumps are the preferred solution. Some potential advantages of that pillar geometry allows a finer pitch interconnect compared to the conventional solder sphere technology. The risk of shorts occurring between bumps during fabrication and flip-chip assembly, such as during electroplating or printing and reflow, is reduced for copper pillar bumps.
Moreover, copper pillar bumps may have a larger stand off compared to solder bumps. This may be a benefit during the underfill process. Less restrictions exist for underfill materials or processes, for example small filler size or capillary underfilling and underfill molding respectively. In addition, due to the larger stand off of copper pillar bumps stress at the chip bump interfaces is reduced due to the higher aspect ratio and higher flexibility of the interconnect element. In particular this becomes important when fragile low k interlayer dielectrics are used. The present invention seeks to alleviate some of the outlaying problems and proposes an economic solution to fabricate bumps with a large pitch and also fine pitch at a low cost.
The known fine pitch bumping technologies, for example solder bumping or copper pillar bumping have the disadvantage that bumps are typically grown by electroplating at relatively low rates, for example at approximately 3 μm/min. This results in very high production costs. In electroplating the uniformity is restricted across the wafer that is greater than 10%. Different diameters of the bumps at the same height are only possible by copper pillar technology. The different feature sizes increase the non-uniformity of copper plating. Special bump area geometries such as bump lines, small rectangular arrays and square arrays can result in different bump heights due to the different current density in electroplating.